ARM Cortex-A53 MPCore

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System Control

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4.4.22 AArch32 Thread registers

Table 4-142 shows the miscellaneous operations. See the ARM

Architecture Reference Manual

ARMv8, for ARMv8-A architecture profile for more information.

4.4.23 AArch32 Performance monitor registers

Table 4-143 shows the performance monitor registers. See the ARM

Architecture Reference

Manual ARMv8, for ARMv8-A architecture profile for more information.

Table 4-142 Miscellaneous System instructions

Name CRn Op1 CRm Op2 Reset Description

TPIDRURW c13 0 c0 2 UNK User Read/Write Thread ID Register

TPIDRURO 3 UNK User Read-Only Thread ID Register

TPIDRPRW 4 UNK EL1 only Thread ID Register

HTPIDR 4 c0 2 UNK Hyp Software Thread ID Register

Table 4-143 Performance monitor registers

Name CRn Op1 CRm Op2 Reset Description

PMCR c9 0 c12 0

0x41033000

Performance Monitors Control Register on page 12-7

PMCNTENSET 1 UNK Performance Monitors Count Enable Set Register

PMCNTENCLR 2 UNK Performance Monitors Count Enable Clear Register

PMOVSR 3 UNK Performance Monitors Overflow Flag Status Register

PMSWINC 4 UNK Performance Monitors Software Increment Register

PMSELR 5 UNK Performance Monitors Event Counter Selection Register

PMCEID0 6

0x63FFFFFF

Performance Monitors Common Event Identification

PMCEID1 7

0x00000000

Performance Monitors Common Event Identification

PMCCNTR c13 0 UNK Performance Monitors Cycle Count Register

PMXEVTYPER 1 UNK Performance Monitors Selected Event Type Register

PMXEVCNTR 2 UNK Performance Monitors Event Count Registers

PMUSERENR c14 0

0x00000000

Performance Monitors User Enable Register

PMINTENSET 1 UNK Performance Monitors Interrupt Enable Set Register

PMINTENCLR 2 UNK Performance Monitors Interrupt Enable Clear Register

PMOVSSET 3 UNK Performance Monitor Overflow Flag Status Set Register

ARM Cortex-A53 MPCore - Page 212