ARM Cortex-A53 MPCore - Page 213

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-152
ID021414 Non-Confidential
4.4.24 AArch32 Secure registers
Table 4-144 shows the Secure registers. See the ARM
®
Architecture Reference Manual ARMv8,
for ARMv8-A architecture profile for more information.
PMEVCNTR0 c14 0 c8 0 UNK Performance Monitors Event Count Register 0
PMEVCNTR1 1 UNK
PMEVCNTR2 2 UNK
PMEVCNTR3 3 UNK
PMEVCNTR4 4 UNK
PMEVCNTR5 5 UNK
PMEVTYPER0 c12 0 UNK Performance Monitors Selected Event Type Register 0
PMEVTYPER1 1 UNK
PMEVTYPER2 2 UNK
PMEVTYPER3 3 UNK
PMEVTYPER4 4 UNK
PMEVTYPER5 5 UNK
PMCCFILTR c15 7
0x00000000 Performance Monitors Cycle Count Filter Register
a. The reset value is 0x623FFFFF if L2 cache is not implemented.
Table 4-143 Performance monitor registers (continued)
Name CRn Op1 CRm Op2 Reset Description
Table 4-144 Security registers
Name CRn Op1 CRm Op2 Reset Description
SCR c1 0 c1 0
0x00000000 Secure Configuration Register on page 4-199
SDER 1 UNK Secure Debug Enable Register
NSACR 2
0x00000000
a
Non-Secure Access Control Register on page 4-202
VBAR c12 0 c0 0
0x00000000 Vector Base Address Register on page 4-263
MVBAR 1 UNK Monitor Vector Base Address Register
ISR c1 0 UNK Interrupt Status Register
a. If EL3 is AArch64 then the NSACR reads as 0x00000C00 .