System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-163
ID021414 Non-Confidential
Table 4-156 shows the ID_PFR1 bit assignments.
To access the ID_PFR1:
MRC p15,0,<Rt>,c0,c1,1 ; Read ID_PFR1 into Rt
Register access is encoded as follows:
4.5.8 Debug Feature Register 0
The ID_DFR0 characteristics are:
Purpose Provides top level information about the debug system in AArch32.
Usage constraints This register is accessible as follows:
Must be interpreted with the Main ID Register, MIDR.
Configurations ID_DFR0 is architecturally mapped to AArch64 register ID_DFR0_EL1.
See AArch32 Debug Feature Register 0 on page 4-19.
There is one copy of this register that is used in both Secure and
Non-secure states.
Table 4-156 ID_PFR1 bit assignments
Bits Name Function
[31:28] GIC CPU GIC CPU support:
0x0
GIC CPU interface is disabled, GICCDISABLE is HIGH.
0x1
GIC CPU interface is enabled, GICCDISABLE is LOW.
[27:20] - Reserved, RAZ.
[19:16] GenTimer Generic Timer support:
0x1
Generic Timer implemented.
[15:12] Virtualization Indicates support for Virtualization:
0x1
Virtualization implemented.
[11:8] MProgMod M profile programmers' model support:
0x0
Not supported.
[7:4] Security Security support:
0x1
Security implemented.This includes support for Monitor mode and the SMC instruction.
[3:0] ProgMod, Indicates support for the standard programmers model for ARMv4 and later.
Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined and System modes:
0x1
Supported.
Table 4-157 ID_PFR1 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 001
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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