System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-226
ID021414 Non-Confidential
Table 4-207 shows the TTBR0 bit assignments when TTBCR.EAE is 1.
To access the TTBR0 when TTBCR.EAE==1:
MRRC p15,0,<Rt>,<Rt2>,c2 ; Read 64-bit TTBR0 into Rt (low word) and Rt2 (high word)
MCRR p15,0,<Rt>,<Rt2>,c2 ; Write Rt (low word) and Rt2 (high word) to 64-bit TTBR0
4.5.41 Translation Table Base Register 1
The TTBR1 characteristics are:
Purpose Holds the base address of translation table 1, and information about the
memory it occupies. This is one of the translation tables for the stage 1
translation of memory accesses from modes other than Hyp mode.
Usage constraints This register is accessible as follows:
Used in conjunction with the TTBCR. When the 64-bit TTBR1 format is
used, cacheability and shareability information is held in the TTBCR and
not in TTBR1. See Translation Table Base Control Register on
page 4-228.
Configurations TTBR1 (NS) is architecturally mapped to AArch64 register TTBR0_EL1.
See Translation Table Base Register 1 on page 4-80.
There are separate Secure and Non-secure copies of this register.
Attributes TTBR1 is:
• A 32-bit register when TTBCR.EAE is 0.
• A 64-bit register when TTBCR.EAE is 1.
There are two formats for this register. TTBCR.EAE determines which format of the register is
used. This section describes:
• TTBR1 format when using the Short-descriptor translation table format on page 4-227.
• TTBR1 format when using the Long-descriptor translation table format on page 4-227.
Table 4-207 TTBR0 bit assignments, TTBRC.EAE is 1
Bits Name Function
[63:56] - Reserved,
RES0.
[55:48] ASID An ASID for the translation table base address. The TTBCR.A1 field selects either TTBR0.ASID or
TTBR1.ASID.
[47:0] BADDR[47:x] Translation table base address, bits[47:x]. Bits [x-1:0] are
RES0.
x is based on the value of TTBCR.T0SZ, and is calculated as follows:
• If TTBCR.T0SZ is 0 or 1, x = 5 - TTBCR.T0SZ.
• If TTBCR.T0SZ is greater than 1, x = 14 - TTBCR.T0SZ.
The value of x determines the required alignment of the translation table, that must be aligned to 2x bytes.
If bits [x-1:3] are not all zero, this is a misaligned Translation Table Base Address. Its effects are
CONSTRAINED UNPREDICTABLE, where bits [x-1:0] are treated as if all the bits are zero. The value read
back from those bits is the value written.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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