System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-227
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TTBR1 format when using the Short-descriptor translation table format
Figure 4-113 shows the TTBR0 bit assignments when TTBCR.EAE is 0.
Figure 4-113 TTBR1 bit assignments, TTBCR.EAE is 0
Table 4-208 shows the TTBR1 bit assignments when TTBCR.EAE is 0.
To access the TTBR1 when TTBCR.EAE is 0:
MRC p15, 0, <Rt>, c2, c0, 1 ; Read TTBR1 into Rt
MCR p15, 0, <Rt>, c2, c0, 1 ; Write Rt to TTBR1
TTBR1 format when using the Long-descriptor translation table format
Figure 4-114 on page 4-228 shows the TTBR1 bit assignments when TTBCR.EAE is 1.
Table 4-208 TTBR1 bit assignments, TTBCR.EAE is 0
Bits Name Function
[31:7] TTB1 Translation table base 1 address, bits[31:x], where x is 14-(TTBCR.N). Bits [x-1:7] are
RES0.
The translation table must be aligned on a 16KByte boundary.
If bits [x-1:7] are not all zero, this is a misaligned Translation Table Base Address. Its effects are
CONSTRAINED
UNPREDICTABLE, where bits [x-1:7] are treated as if all the bits are zero. The value read back from those bits is
the value written.
[6] - Reserved,
RES0.
[5] NOS Not Outer Shareable bit. Indicates the Outer Shareable attribute for the memory associated with a translation
table walk that has the Shareable attribute, indicated by TTBR0.S is 1. The possible values are:
0
Outer Shareable.
1
Inner Shareable.
This bit is ignored when TTBR0.S is 0.
[4:3] RGN Region bits. Indicates the Outer cacheability attributes for the memory associated with the translation table
walks. The possible values are:
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Cacheable.
0b11
Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[2] IMP Reserved,
RES0.
[1] S Shareable bit. Indicates the Shareable attribute for the memory associated with the translation table walks. The
possible values are:
0
Non-shareable.
1
Shareable.
[0] C Cacheable bit. Indicates whether the translation table walk is to Inner Cacheable memory.
0
Inner Non-cacheable
1
Inner Cacheable.
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