ARM Cortex-A53 MPCore - Page 291

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-230
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Figure 4-116 TTBCR bit assignments, TTBCR.EAE is 1
Table 4-211 shows the TTBCR bit assignments when TTBCR.EAE is 1.
31 30 29 28 27 26 25 24 23 22 21 19 18 16 15 14 13 12 11 10 9 8 7 6 3 2
SH1 A1 T1SZ SH0 RES 0 TDSZ
EAE
EPD0
0
RES
0
ORGN1
IRGN1
EPD1
IRGN0
ORGN0
RES 0 RES 0
Table 4-211 TTBCR bit assignments, TTBCR.EAE is 1
Bits Name Function
[31] EAE Extended Address Enable:
1 Use the 40-bit translation system, with the Long-descriptor translation table format.
[30] - Reserved,
RES0.
[29:28] SH1 Shareability attribute for memory associated with translation table walks using TTBR1:
0b00 Non-shareable.
0b10 Outer Shareable.
0b11 Inner Shareable.
Other values are reserved.
Resets to 0.
[27:26] ORGN1 Outer cacheability attribute for memory associated with translation table walks using TTBR1:
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
Resets to 0.
[25:24] IRGN1 Inner cacheability attribute for memory associated with translation table walks using TTBR1:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
Resets to 0.
[23] EPD1 Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk
is performed on a TLB miss, for an address that is translated using TTBR1:
0 Perform translation table walks using TTBR1.
1 A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No
translation table walk is performed.