System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-231
ID021414 Non-Confidential
To access the TTBCR:
MRC p15,0,<Rt>,c2,c0,0 ; Read TTBR0 into Rt
MCR p15,0,<Rt>,c2,c0,0 ; Write Rt to TTBR0
[22] A1 Selects whether TTBR0 or TTBR1 defines the ASID:
0
TTBR0.ASID defines the ASID.
1
TTBR1.ASID defines the ASID.
[21:19] - Reserved,
RES0.
[18:16] T1SZ
The size offset of the memory region addressed by TTBR1. The region size is 2
32-T1SZ
bytes.
Resets to 0.
[15:14] - Reserved,RES0.
[13:12] SH0 Shareability attribute for memory associated with translation table walks using TTBR0:
0b00
Non-shareable.
0b10
Outer Shareable.
0b11
Inner Shareable.
Other values are reserved.
Resets to 0.
[11:10] ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0:
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Cacheable.
0b11
Normal memory, Outer Write-Back no Write-Allocate Cacheable.
Resets to 0.
[9:8] IRGN0 Inner cacheability attribute for memory associated with translation table walks using TTBR0:
0b00
Normal memory, Inner Non-cacheable.
0b01
Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Inner Write-Through Cacheable.
0b11
Normal memory, Inner Write-Back no Write-Allocate Cacheable.
Resets to 0.
[7] EPD0 Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk
is performed on a TLB miss, for an address that is translated using TTBR0:
0
Perform translation table walks using TTBR0.
1
A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No
translation table walk is performed.
[6:3] - Reserved,
RES0.
[2:0] T0SZ
The size offset of the memory region addressed by TTBR0. The region size is 2
32-T0SZ
bytes.
Resets to 0.
Table 4-211 TTBCR bit assignments, TTBCR.EAE is 1 (continued)
Bits Name Function
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