System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-232
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4.5.43 Hyp Translation Control Register
The HTCR characteristics are:
Purpose Controls translation table walks required for the stage 1 translation of
memory accesses from Hyp mode, and holds cacheability and shareability
information for the accesses.
Usage constraints This register is accessible as follows:
Configurations HTCR is architecturally mapped to AArch64 register TCR_EL2. See
Translation Control Register, EL2 on page 4-89.
Attributes HTCR is a 32-bit register.
Figure 4-117 shows the HTCR bit assignments.
Figure 4-117 HTCR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
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