System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-233
ID021414 Non-Confidential
Table 4-212 shows the HTCR bit assignments.
The processor does not use the implementation-defined bit, HTCR[30], so this bit is
RES0.
To access the HTCR:
MRC p15, 4, <Rt>, c2, c0, 2; Read HTCR into Rt
MCR p15, 4, <Rt>, c2, c0, 2; Write Rt to HTCR
4.5.44 Virtualization Translation Control Register
The VTCR characteristics are:
Purpose Controls the translation table walks required for the stage 2 translation of
memory accesses from Non-secure modes other than Hyp mode, and holds
cacheability and shareability information for the accesses.
Usage constraints This register is accessible as follows:
Table 4-212 HTCR bit assignments
Bits Name Function
[31] - Reserved,
RES1.
[30:24] - Reserved,
RES0.
[23] - Reserved,
RES1.
[22:14] - Reserved,
RES0.
[13:12] SH0 Shareability attribute for memory associated with translation table walks using TTBR0. The possible values are:
0b00
Non-shareable.
0b01
Reserved.
0b10
Outer shareable.
0b11
Inner shareable.
[11:10] ORGN0 Outer cacheability attribute for memory associated with translation table walks using TTBR0. The possible
values are:
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Cacheable.
0b11
Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0 Inner cacheability attribute for memory associated with translation table walks using TTBR0. The possible
values are:
0b00
Normal memory, Inner Non-cacheable.
0b01
Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10
Normal memory, Inner Write-Through Cacheable.
0b11
Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:3] - Reserved,
RES0.
[2:0] T0SZ
Size offset of the memory region addressed by TTBR0. The region size is 2
(32-TSIZE)
bytes.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
To Next Page
Loading...
