ARM Cortex-A53 MPCore - Page 363

Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-19
ID021414 Non-Confidential
[6] Device 0
Non-coherent, Outer WB
Non-coherent, Outer NC 1
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB Transient:
0 Non-transient
1 Transient.
[5:4] Device Stage 1 (Non-device) overridden by stage 2 (Device)
00 Not overridden
01 Overridden.
Non-coherent, Outer WB Inner type:
10 NC.
11 WT.
Non-coherent, Outer NC
11
Non-coherent, Outer WT Inner type:
00 NC.
01 WB.
10 WT.
Coherent, Inner WB and Outer WB Inner allocation hint:
00 NA.
01 WA .
10 RA.
11 WRA.
[3:2] Device Device type:
00 nGnRnE.
01 nGnRE.
10 nGRE.
11 GRE.
Non-coherent, Outer WB Outer allocation hint:
00 NA.
01 WA .
10 RA.
11 WRA.
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB
Non-coherent, Outer NC Inner type:
00 NC.
01 WB.
10 WT.
11 Unused.
Table 6-14 Main TLB memory types and shareability (continued)
Bits Memory type Description