Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-20
ID021414 Non-Confidential
Walk cache RAM
The walk cache RAM uses 117-bit encoding when parity is enabled and 114-bit encoding when
parity is disabled. Table 6-15 shows the data fields in the walk cache descriptor.
[1:0] Device Shareability
00
Non-shareable.
01
Unused.
10
Outer shareable.
11
Inner shareable.
Non-coherent, Outer WB
Non-coherent, Outer NC
Non-coherent, Outer WT
Coherent, Inner WB and Outer WB
Table 6-14 Main TLB memory types and shareability (continued)
Bits Memory type Description
Table 6-15 Walk cache descriptor fields
Bits Name Description
[116:114] ECC ECC. If ECC is not configured, these bits are absent.
[113:84] PA Physical Address of second, last translation level.
[83:60] VA Virtual address.
[59:56] - Reserved, must be zero.
[55:40] ASID Address Space Identifier.
[39:22] VMID Virtual Machine Identifier.
[31] NS, walk Security state that the entry was fetched in.
[30:22] - Reserved, must be zero.
[21:18] Domain Valid only if the entry was fetched in VMSAv7 format.
[17:16] Entry size Memory size to which entry maps:
0b00
1MB.
0b01
2MB.
0b10
512MB.
0b11
Unused.
[15] NSTable Combined NSTable bits from first and second level stage 1 tables or NS descriptor (VMSA).
[14] PXNTable Combined PXNTable bits from stage1 descriptors up to last level.
[13] XNTable Combined XNTable bit from stage1 descriptors up to last level.
[12:11] APTable Combined APTable bits from stage1 descriptors up to last level.
[10] EL3 Set if the entry was fetched in AArch64 EL3 mode.
[9] EL2 Set if the entry was fetched in EL2 mode.
[8:1] Attrs Physical attributes of the final level stage 1 table.
[0] Valid Valid bit:
0
Entry does not contain valid data.
1
Entry contains valid data.
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