Level 1 Memory System
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 6-21
ID021414 Non-Confidential
IPA cache RAM
The Intermediate Physical Address (IPA) cache RAM uses a 117-bit encoding when parity is
enabled and 114-bit encoding when parity is disabled. Table 6-16 shows the data fields in the
IPA cache descriptor.
Table 6-16 IPA cache descriptor fields
Bits Name Description
[116:114] ECC ECC. If ECC is not configured, these bits are absent.
[113:86] PA Physical address.
[85:62] IPA Unused lower bits, page size dependent, must be zero.
[61:59] - Reserved, must be zero.
[58:56] Size The size values are:
0b011
64KB.
0b101
2MB.
0b111
512MB.
[55:40] - Reserved, must be zero.
[39:32] VMID Virtual Machine Identifier.
[31:11] - Reserved, must be zero.
[10] Contiguous Set if the pagewalk had contiguous bit set.
[9:6] Memattrs Memory attributes.
[5] XN Execute Never.
[4:3] HAP Hypervisor access permissions.
[2:1] SH Shareability.
[0] Valid The entry contains valid data.
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