Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-29
ID021414 Non-Confidential
Figure 11-12 EDPIDR1 bit assignments
Table 11-17 shows the EDPIDR1 bit assignments.
The EDPIDR1 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE4
.
Peripheral Identification Register 2
The EDPIDR2 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The EDPIDR2 is in the Debug power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-13 shows the EDPIDR2 bit assignments.
Figure 11-13 EDPIDR2 bit assignments
Table 11-17 EDPIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] DES_0
0xB
ARM Limited. This is the least significant nibble of JEP106 ID code.
[3:0] Part_1
0xD
Most significant nibble of the debug part number.
Off DLK OSLK EDAD SLK Default
-- - - - RO
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