Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-30
ID021414 Non-Confidential
Table 11-18 shows the EDPIDR2 bit assignments.
The EDPIDR2 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFE8
.
Peripheral Identification Register 3
The EDPIDR3 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The EDPIDR3 is in the Debug power domain.
Attributes See the register summary in Table 11-11 on page 11-21.
Figure 11-14 shows the EDPIDR3 bit assignments.
Figure 11-14 EDPIDR3 bit assignments
Table 11-19 shows the EDPIDR3 bit assignments.
The EDPIDR3 can be accessed through the internal memory-mapped interface and the external
debug interface, offset
0xFEC
.
Table 11-18 EDPIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Revision
0x2
r0p2.
[3] JEDEC
0b1
RAO. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011
ARM Limited. This is the most significant nibble of JEP106 ID code.
Off DLK OSLK EDAD SLK Default
-- - - - RO
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