Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-49
ID021414 Non-Confidential
Table 11-37 shows the ROMPIDR4 bit assignments.
The ROMPIDR4 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFD0
.
Peripheral Identification Register 5-7
No information is held in the Peripheral ID5, Peripheral ID6 and Peripheral ID7 Registers. They
are reserved for future use and are
RES0.
11.11.5 Component Identification Registers
There are four read-only Component Identification Registers, Component ID0 through
Component ID3. Table 11-38 shows these registers.
The Component Identification Registers identify Debug as an ARM Debug Interface v5
component. The ROM table Component ID registers are:
• Component Identification Register 0.
• Component Identification Register 1 on page 11-50.
• Component Identification Register 2 on page 11-51.
• Component Identification Register 3 on page 11-51.
Component Identification Register 0
The ROMCIDR0 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Table 11-37 ROMPIDR4 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] Size
0x0
Size of the component. Log2 the number of 4KB pages from the start of the component to the end
of the component ID registers.
[3:0] DES_2
0x4
Designer, JEP106 continuation code, least significant nibble. For ARM Limited.
Table 11-38 Summary of the ROM table component Identification registers
Register Value Offset
ROMCIDR0
0x0D 0xFF0
ROMCIDR1
0x10 0xFF4
ROMCIDR2
0x05 0xFF8
ROMCIDR3
0xB1 0xFFC
Off DLK OSLK EDAD SLK Default
-- - - - RO
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