ARM Cortex-A53 MPCore - Page 452

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-50
ID021414 Non-Confidential
Configurations The ROMCIDR0 is in the Debug power domain.
Attributes See the register summary in Table 11-28 on page 11-41.
Figure 11-27 shows the ROMCIDR0 bit assignments.
Figure 11-27 ROMCIDR0 bit assignments
Table 11-39 shows the ROMCIDR0 bit assignments.
The ROMCIDR0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFF0 .
Component Identification Register 1
The ROMCIDR1 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The ROMCIDR1 is in the Debug power domain.
Attributes See the register summary in Table 11-28 on page 11-41.
Figure 11-28 shows the ROMCIDR1 bit assignments.
Figure 11-28 ROMCIDR1 bit assignments
RES0
31 0
PRMBL_0
78
Table 11-39 ROMCIDR0 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] Size
0x0D Preamble byte 0.
Off DLK OSLK EDAD SLK Default
-- - - - RO
RES0
31 0
PRMBL_1
78
34
CLASS