ARM Cortex-A53 MPCore - Page 453

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-51
ID021414 Non-Confidential
Table 11-40 shows the ROMCIDR1 bit assignments.
The ROMCIDR1 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFF4 .
Component Identification Register 2
The ROMCIDR2 characteristics are:
Purpose Provides information to identify an external debug component.
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The ROMCIDR2 is in the Debug power domain.
Attributes See the register summary in Table 11-28 on page 11-41.
Figure 11-29 shows the ROMCIDR2 bit assignments.
Figure 11-29 ROMCIDR2 bit assignments
Table 11-41 shows the ROMCIDR2 bit assignments.
The ROMCIDR2 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFF8 .
Component Identification Register 3
The ROMCIDR3 characteristics are:
Purpose Provides information to identify an external debug component.
Table 11-40 ROMCIDR1 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:4] CLASS
0x1 Component Class. For a ROM table.
[3:0] PRMBL_1
0x0 Preamble.
Off DLK OSLK EDAD SLK Default
-- - - - RO
RES0
31 0
PRMBL_2
78
Table 11-41 ROMCIDR2 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] PRMBL_2
0x05 Preamble byte 2.