ARM Cortex-A53 MPCore - Page 454

Debug
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 11-52
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Table 11-1 on page 11-5 describes the condition codes.
Configurations The ROMCIDR3 is in the Debug power domain.
Attributes See the register summary in Table 11-28 on page 11-41.
Figure 11-30 shows the ROMCIDR3 bit assignments.
Figure 11-30 ROMCIDR3 bit assignments
Table 11-42 shows the ROMCIDR3 bit assignments.
The ROMCIDR3 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xFFC .
Off DLK OSLK EDAD SLK Default
-- - - - RO
RES0
31 0
PRMBL_3
78
Table 11-42 ROMCIDR3 bit assignments
Bits Name Function
[31:8] - Reserved,
RES0.
[7:0] PRMBL_3
0xB1 Preamble byte 3.