ARM Cortex-A53 MPCore - Page 464

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-10
ID021414 Non-Confidential
Table 12-6 PMU common events
Bit
Event
number
Event mnemonic Description
[31]
0x1F L1D_CACHE_ALLOCATE L1 Data cache allocate:
0 This event is not implemented.
[30]
0x1E CHAIN Chain. For odd-numbered counters, counts once for each overflow of the
preceding even-numbered counter. For even-numbered counters, does not
count:
1 This event is implemented.
[29]
0x1D BUS_CYCLES Bus cycle:
1 This event is implemented.
[28]
0x1C TTBR_WRITE_RETIRED TTBR write, architecturally executed, condition check pass - write to
translation table base:
0 This event is not implemented.
[27]
0x1B INST_SPEC Instruction speculatively executed:
0 This event is not implemented.
[26]
0x1A MEMORY_ERROR Local memory error:
1 This event is implemented.
[25]
0x19 BUS_ACCESS Bus access:
1 This event is implemented.
[24]
0x18 L2D_CACHE_WB L2 Data cache Write-Back:
0 This event is not implemented if the Cortex-A53 processor
has been configured without an L2 cache.
1 This event is implemented if the Cortex-A53 processor has
been configured with an L2 cache.
[23]
0x17 L2D_CACHE_REFILL L2 Data cache refill:
0 This event is not implemented if the Cortex-A53 processor
has been configured without an L2 cache.
1 This event is implemented if the Cortex-A53 processor has
been configured with an L2 cache.
[22]
0x16 L2D_CACHE L2 Data cache access:
0 This event is not implemented if the Cortex-A53 processor
has been configured without an L2 cache.
1 This event is implemented if the Cortex-A53 processor has
been configured with an L2 cache.
[21]
0x15 L1D_CACHE_WB L1 Data cache Write-Back:
1 This event is implemented.
[20]
0x14 L1I_CACHE L1 Instruction cache access:
1 This event is implemented.
[19]
0x13 MEM_ACCESS Data memory access:
1 This event is implemented.
[18]
0x12 BR_PRED Predictable branch speculatively executed:
1 This event is implemented.
[17]
0x11 CPU_CYCLES Cycle:
1 This event is implemented.