ARM Cortex-A53 MPCore - Page 465

Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-11
ID021414 Non-Confidential
To access the PMCEID0_EL0 in AArch64 Execution state, read or write the register with:
[16] 0x10 BR_MIS_PRED Mispredicted or not predicted branch speculatively executed:
1 This event is implemented.
[15]
0x0F UNALIGNED_LDST_RETIRED Instruction architecturally executed, condition check pass - unaligned load or
store:
1 This event is implemented.
[14]
0x0E BR_RETURN_RETIRED Instruction architecturally executed, condition check pass - procedure return:
0 This event is not implemented.
[13]
0x0D BR_IMMED_RETIRED Instruction architecturally executed - immediate branch:
1 This event is implemented.
[12]
0x0C PC_WRITE_RETIRED Instruction architecturally executed, condition check pass - software change
of the PC:
1 This event is implemented.
[11]
0x0B CID_WRITE_RETIRED Instruction architecturally executed, condition check pass - write to
CONTEXTIDR:
1 This event is implemented.
[10]
0x0A EXC_RETURN Instruction architecturally executed, condition check pass - exception return:
1 This event is implemented.
[9]
0x09 EXC_TAKEN Exception taken:
1 This event is implemented.
[8]
0x08 INST_RETIRED Instruction architecturally executed:
1 This event is implemented.
[7]
0x07 ST_RETIRED Instruction architecturally executed, condition check pass - store:
1 This event is implemented.
[6]
0x06 LD_RETIRED Instruction architecturally executed, condition check pass - load:
1 This event is implemented.
[5]
0x05 L1D_TLB_REFILL L1 Data TLB refill:
1 This event is implemented.
[4]
0x04 L1D_CACHE L1 Data cache access:
1 This event is implemented.
[3]
0x03 L1D_CACHE_REFILL L1 Data cache refill:
1 This event is implemented.
[2]
0x02 L1I_TLB_REFILL L1 Instruction TLB refill:
1 This event is implemented.
[1]
0x01 L1I_CACHE_REFILL L1 Instruction cache refill:
1 This event is implemented.
[0]
0x00 SW_INCR Instruction architecturally executed, condition check pass - software
increment:
1 This event is implemented.
Table 12-6 PMU common events (continued)
Bit
Event
number
Event mnemonic Description