Performance Monitor Unit
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 12-12
ID021414 Non-Confidential
MRS <Xt>, PMCEID0_EL0; Read Performance Monitor Common Event Identification Register 0
To access the PMCEID0 in AArch32 Execution state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c9, c12, 6; Read Performance Monitor Common Event Identification
Register 0
The PMCEID0_EL0 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0xE20
.
12.4.3 Performance Monitors Common Event Identification Register 1
The PMCEID1_EL0 characteristics are:
Purpose Defines which common architectural and common microarchitectural
feature events are implemented.
Usage constraints This register is accessible as follows:
This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.
Configurations The PMCEID1_EL0 is architecturally mapped to:
• The AArch32 register PMCEID1. See Performance Monitors
Common Event Identification Register 1 on page 12-21.
• The external register PMCEID1_EL0.
Attributes PMCEID1_EL0 is a 32-bit register.
Figure 12-4 shows the PMCEID1_EL0 bit assignments.
Figure 12-4 PMCEID1 bit assignments
Table 12-7 shows the PMCEID1_EL0 bit assignments.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config RO RO RO RO RO
Table 12-7 PMCEID1 bit assignments
Bits Name Function
[31:1] -
[32] CE[32] Common architectural and microarchitectural feature events that can be counted by the PMU event counters.
For each bit described in Table 12-8 on page 12-13, the event is implemented if the bit is set to 1, or not
implemented if the bit is set to 0.
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