ARM Cortex-A53 MPCore - Page 531

Embedded Trace Macrocell
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 13-36
ID021414 Non-Confidential
Table 13-29 shows the TRCIDR10 bit assignments.
The TRCIDR10 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x188 .
13.8.27 ID Register 11
The TRCIDR11 characteristics are:
Purpose Returns the number of special P1 right-hand keys that the trace unit can
use.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-29 shows the TRCIDR11 bit assignments.
Figure 13-29 TRCIDR11 bit assignments
Table 13-30 shows the TRCIDR11 bit assignments.
The TRCIDR11 can be accessed through the internal memory-mapped interface and the
external debug interface, offset
0x18C .
13.8.28 ID Register 12
The TRCIDR12 characteristics are:
Purpose Returns the number of conditional instruction right-hand keys that the
trace unit can use.
Usage constraints There are no usage constraints.
Configurations Available in all configurations.
Attributes See the register summary in Table 13-3 on page 13-10.
Figure 13-30 on page 13-37 shows the TRCIDR12 bit assignments.
Table 13-29 TRCID10 bit assignments
Bits Name Function
[31:0] NUMP1KEY The number of P1 right-hand keys that the trace unit can use.
0 Number of P1 right-hand keys.
31 0
NUMP1SPC
Table 13-30 TRCID11 bit assignments
Bits Name Function
[31:0] NUMP1SPC The number of special P1 right-hand keys that the trace unit can use.
0 Number of special P1 right-hand keys.