COBHAM GR740 User Manual

GR740-UM-DS, Nov 2017, Version 1.7 12 www.cobham.com/gaisler
GR740
1.7 2017 November Updated ordering information in section 42.
Updated placement diagram under section 40.
Add new package drawings in section 40.4.
Add information on booting over RMAP, changes in sections 1.7 and 5.3.
Add information about bridges, posted writes and AMBA ERROR response propagation to
sections 2.3, 5.10, 6.2.13, 6.3.5, 6.7.4, 10.5.1, 13.4.4.9, 13.4.5.7.2, 14.3.3, 14.4.4, 15.4.4,
16.4.5, 17.6.6, 19.7.1, 19.7.2, 19.8, 19.9, 35.5.9, 35.6.7, 35.7.2, 35.8.2, 35.9, 37.2.2.
Add information on PROM EDAC handling with multiple external devices in section 1.7
and 19.7.1.
Change errata section 43 to also include design changes between silicon revisions. Update
and add additional errata descriptions. Add silicon revision 1 column in table 602.
Document new L2 cache register fields in section 9.4. 
Add partial WRPSR description to LEON4 section 6.2.16.
Extend LEON4 MMU TLB disable description in section 6.10.8.
Describe new IRQMP boot/monitor interface in sections 21.2.10 and 21.3.
Update GRGPIO interrupt flag register description in section 22.3.10.
Added description of AHB status register multiple error logging and filtering in section 27.
Correct number of up-counter bits in section 5.9.2.
Clarify timetag counter behaviour in sections 6.10.4 and 36.1.
Document PCI controller DFA bit in section 15.10.1.
Clarify PCI target supported byte-enables in section 15.5.3.
Update PCI DMA controller description in section 15.6.3.
Update register for bootstrap signals description in section 28.3 for silicon revision 1.
Add reference to GRLIB-AN-0004 in sections 1.7 and 6.11.4.
Indicate AHB and instruction trace buffer sizes in section 2.1.
Add note about using the MMU to mark memory as cacheable in section 6.3.6.
Describe SDRAM bus parking functionality in section 10.6.2.
Update description of SDRAM controller BANKSZ field in section 10.6.1.
Clarifications about internal and external SDRAM banks under section 10.
Update SpaceWire router configuration port memory range in sections 2.3 and 13.5.3.
Document SpaceWire router AMBA port interrupt in section 2.4 and table 193.
Describe SpaceWire TDP functionality added for silicon revision 1 in sections 3.1, 5.9.2, and
31.
Added information on SpaceWire receive rate in section 13.3.1.2. Clarify that t
SPW4
and
t
SPW5
in table 587 are valid assuming use of SpW PLL in nominal mode.
Extend section 5.5 ASMP configurations to 5.5 Separation and ASMP configurations.
Add description of LEON4 %ASR16 register in section 6.10.2.
Updated LEON4 %ASR17 description in section 6.10.3.
Corrected range and recommended values of RTR.AMBADMACTRL.INTNUM register in
table 160.
Corrected range of RTR.ICODEGEN.IN register in table 193.
Update temperature sensor controller documentation in section 29.
Corrected field ranges in SPI controller mode register description in table 421.
Updated package references to CCGA/LGA on front page and in sections 40 and 42.
Update processor status monitoring description in 21.2.4.
Clarify that PROC_ERRORN is connected to processor 0 only, in section 6.2.13
Clarify bootstrap signal effects in section 3.1. Clarify that GPIO[7:6] are still used to disable
EDCL 1. Update clock gate unit conditions in section 25.
Add GRLIB-TN-0013 issue in section 43.2.27.
Clarify that WDOGN and ERRORN are open-drain in tables 28 and 597. 
Updated Absolute Maximum Ratings and recommended operating conditions, adding over-
shoot specifications, in section 39.
Table 1. Change record
Version Date Note

COBHAM GR740 Specifications

General

Brand	COBHAM
Model	GR740
Category	Computer Hardware
Language	English