Hioki 3560 - Status Byte Registers

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8.2 Operating Procedure (GP-IB)
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8
.2.12 Status Byte Registers
Not use
d
N
ot use
d
N
ot use
d
MSS
RQS
ESB MAV
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Logical sum
＆
＆
bit3
bit1
bit0
ESB MAV
bit5
bit4
N
ot use
d
×
bit7
bit6
Status byte registers（STB）
Service request enable registers
（
SRER
）
N
ot use
d
N
ot use
d
Not use
d
Not use
d
Not use
d
Not use
d
bit2
Bit Meaning
7
Not used
6
RQS
RQS is set to "1" after the service request is sent.
MSS
MSS shows the logical sum of other bits in the status byte
register.
5
ESB
Standard event summary (logical sum) bit
ESB shows the logical sum of the standard event status
register.
4
MAV
Message available
MAV indicates the output queue has messages.
3
Not used
2
Not used
1
Not used
(1) Status byte register (STB)
The status byte register is an 8-bit register whose contents are output
from the 3560 to the controller, when serial polling is being performed.
If even only one bit in the status byte register has changed from 0 to 1
(provided that it is a bit which has been set in the service request enable
register as a bit which can be used), then the MSS bit is set to 1.
Simultaneously with this the SRQ bit is set to 1, and service request is
generated.
The RQS bit is synchronized with service requests, and is read out and
simultaneously cleared when serial polling is being performed. Although
the MSS bit is only read out on an *STB? query, on a *CLS command for
example it is not cleared until the event is cleared.
(2) Service request enable register (SRER)
This register masks the status byte register. Setting a bit of this register
to 1 enables the corresponding bit of the status byte register to be used.