Hioki 3560 - Event Registers

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8.2 Operating Procedure (GP-IB)
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8
.2.13 Event Registers
bit2
DDE
URQ
CME EXE
bit6
bit5
bit4
bit3
Logical sum
＆
＆
bit3
bit1
CME EXE
bit5
bit4
PON URQ
bit7
bit6
Status byte registers（STB）
Service request enable register
（SRER）
DDE QYE RQC OPC
QYE RQC OPCPON
＆
＆
＆
＆
＆
＆
ESB
RQS
MSS
bit6
bit5
bit7
bit2
bit1
bit0
bit0
(1) Standard event status register (SESR)
The standard event status register is an 8-bit register. If any bit in the
standard event status register is set to 1 (after masking by the standard
event status enable register), bit 5 (ESB) of the status byte register is set
to 1.
The standard event status register is cleared in the following three
situations:
When a *CLS command is received.
When an *ESR? query is received.
When the instrument is powered on.