3 Device AGP MotherBoard Design
3-2
Intel740™ Graphics Accelerator Design Guide
•
Intergrated IDE Controller with Ultra DMA/33 support
— PIO mode 4 transfers
— PCI IDE Bus Master Support
•
Intergrated Universal Serial Bus (USB) Controller with 2 USB ports
•
Intergrated System Power Management Support
•
On-board Floppy, Serial, Parallel Ports,
•
Intel 740 Graphics Accelerator
— Accelerated Graphics Port (AGP) Interface
— Memory
100 MHz SDRAM or SGRAM Support
2,4 MB Solder-Down Option
3.1.2 About This Chapter
This chapter is intended for hardware design engineers who are experienced in the design of PC
motherboards or memory subsystem. This document is organized as follows:
•
Section 1, "Introduction"—This section provides an overview of the features of a 3-point AGP
reference design (DS1P/440BX/I740). Chapter 1 also provides a general component overview
of the Pentium II processor, Intel 440BX AGPset, and the Intel 740 graphics accelerator. This
section also provides implementation issues associated with a 3-point AGP design and design
recommendations which Intel feels will provide flexibility to cover a broader range of
products within a market segment.
•
Section 3.2, "3 Device AGP Motherboard Layout and Routing Guidelines"—This section
provides detailed layout, routing, and placement guidelines for the AGP bus and local memory
subsystem. Design guidelines for other buses (Host GTL+, PCI, and DRAM) are covered in
the Intel 440BX AGPset design guidelines.
•
Section 3.3, "3 Device AGP Motherboard Reference Design Schematics"—This chapter
provides the schematics used in the reference design.
3.1.3 Block Diagram
Figure 3-1 shows a block diagram of a typical platform based on the Intel 440BX AGPset with the
Intel740 graphics accelerator. The 82443BX system bus interface supports up to two Pentium II
processors at the maximum bus frequency of 100 MHz. The physical interface design is based on
the GTL+ specification and is compatible with the Intel 440BX AGPset solution. The 82443BX
provides an optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports
3.3V DRAM technologies.