Intel740™ Graphics Accelerator Design Guide
3-21
3 Device AGP MotherBoard Design
3.2.4.1 3 Device AGP Intel740™ Graphics Accelerator Memory
Configurations
In the following discussion the term row refers to a set of memory devices that are simultaneously
selected by an SRAS and the CS# signal.
Configuration #1: In this configuration, the minimum amount of memory (2MB) is supported.
Note that, the same copy of all control signals goes to each component.
Figure 3-20. Memory Layout Dimensions (RCLK and OCLK to RCLK)
Intel740™
Chip
1.0 ±0.25"
33
OCLK
RCLK0
RCLK1
33
3.0 ±0.25"
3.0 ±0.25"
Figure 3-21. 2/4 MB Local Memory Connection (64-bit data path)
Intel740
MD[63:0]
CSx[A:B]# DQM[3:0] DQM[7:4] RCLKx OCLK
MA[11:0]
WEA#
SRASA#
SCASA#
TCLKA
WEA#
SRASA#
SCASA#
TCLKA
256K/512K X 32
256K/512K X 32
CS0A#
CS0A#
MD[31:0]
MD[63:32]
Intel740™ Chip
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