Intel 740 - Device Data Load Topology (Solution 1 Is Shown); Device Strobe Load Topology (Solution 1 Is Shown); Clock Topology and Matching

Intel740™ Graphics Accelerator Design Guide 3-17
3 Device AGP MotherBoard Design
Assume: GAD1 segment A=4.1" segment B=2.7" (A+B=6.8") and GAD2 segment A=3.5" and
segment B=3.0" (A+B=6.5"). Notice that GAD1 A and GAD2 have more than 0.5" difference, but
A+B is only 0.3" difference. Also, the strobes should be the longest signal in the group.
Clock Solutions
Figure 3-13. 3 Device Data Load Topology (Solution 1 is Shown)
Figure 3-14. 3 Device Strobe Load Topology (Solution 1 is shown)
82443BX Segment A Connector
Segment B
Intel740™
Chip
Segment D
Segment C
AGP
Master
Motherboard Add - In Card
3.5" - 5.5"
0.4" - 0.9"
0" - 3.0"
2.0" - 3.0"
82443BX Segment A Connector
Segment B
Intel740™
Chip
Segment D
Segment C
AGP
Master
Motherboard Add - In Card
3.5" - 5.5"
0.4" - 0.9"
0" - 3.0"
2.0" - 3.0"
Figure 3-15. Clock Topology and Matching
Clock Gen
Load 2
Connector
0.3" - 0.4"
0.4" - 0.5"
0.4" - 0.5"
Load 1
Load 3
6.2" - 6.4"
6.4" - 6.6"
4.4" - 4.6"
Gclks
Gclk740
Gclkin
Rs
Rs
Rs