3 Device AGP MotherBoard Design
3-22
Intel740™ Graphics Accelerator Design Guide
3.3 3 Device AGP Motherboard Reference Design
Schematics
This section provides schematics for the 3-point AGP reference design. The description of each
schematic page is named by the logic block shown on that page.
Cover Sheet P-1
The Cover Sheet shows the Schematic page titles, page numbers and disclaimers.
Block Diagram P-2
This page shows a block diagram overview of the Pentium
®
II / Intel
®
440BX AGPset/ Intel
®
740
system design. Also included are page numbers for every major component in the design.
Pentium
®
II Slot 1 processor connector (part 1) P-3
This page shows the first part of the DS1P connector (up to the key). SLP# connection comes
directly from the PIIX4E. Intel recommends placing 0 ohm resistors on the EMI signals. A thermal
sensor (the MAX 1617 ME) which connects to an internal processor diode has been included to
monitor processor temperature.
Pentium
®
II Slot 1 processor connector (part 2) P-4
This page shows the remaining part DS1P connector. Also shown are the optional connections for
overriding the VID pins from the processor.
Clock Synthesizer and ITP connector P-5
This page shows the new clock synthesizer component the CK100 plus recommended decoupling.
The clock synthesizer components must meet all of the system bus, PCI and other system clock
requirements. Several vendors offer components that can be used in this design.
This page also shows the In Target Probe (ITP) Connector. The ITP connector is recommended in
order to use the In Target Probe tool available from Intel and other tool vendors for Pentium II
processor based platform debug.
Note: Some logic analyzer vendors also support the use of the ITP connector. This connector is optional.
It is recommended to design these headers into the system for initial system debug and
development, and leave the connector footprints unpopulated for production.
82443BX Component (System bus and DRAM Interfaces)P-6
This page shows the 82443BX component, System bus and DRAM Interfaces. The 82443BX
connects to the lower 32 bits of the CPU address bus and the CPU control signals, and generates
DRAM control signals for the memory interface. In this design, the 82443BX is configured to
interface to a memory array of 3 DIMMs.
The CKBF is also shown on this page. The 82443BX delivers a single SDRAM clock to the CKBF
which is a 18 output buffer, with an I2C interface which may be used to disable unused clock
outputs for EMI reduction. It outputs 4 clocks to each DIMM socket, and 1 back to the 82443BX
for data timings.
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