Intel740™ Graphics Accelerator Design Guide
3-25
3 Device AGP MotherBoard Design
packs to as short of a trace as possible before routing to the V
TT
plane. If the V
TT
plane is on an
inner layer, keep the trace distance to the via as short as possible by placing the via between pins 6
and 7 for each resistor package. Where this is not possible, use multiple vias to the V
TT
plane for
each group of 4 signals. Refer to the GTL+ Specification for more complete details on GTL+
signaling.
Pull-up and Pull-down Resistors P-28/29
These pages show pull-up and pull-down resistors for PCI signals, PIIX4E, Slot 1(CMOS), ISA,
and AGP signals. Also shown are spare gates.
Decoupling Capacitors P-30/31
Decoupling Caps P-32
These pages show de-coupling capacitance used in the schematics as well as the voltage dividers
used to provide the GTL reference voltage.
Hardware system manager P-33
The LM79 is a hardware system monitor. It monitors voltage regulation, fan RPM and stores POST
codes. The device can be accessed via the X-Bus bus or through the PIIX4E SMBus interface. Note
the voltage level translation circuitry between the 5-Volt LM79 and the rest of the 3.3-Volt
SMBus.
Intel740™ Graphics Accelerator P-34/35
This page shows all of the connections to the Intel740 graphics accelerator. Each Intel740 graphics
accelerator interface is hooked up in this reference design. Beginning in the upper left hand corner
of the page, the video capture port is shown. Internally, the input pins are pulled down. These pins
contain a strapping option for subsystem ID. In this case, the reference design has an ID of 0100h.
Bits that should be a “1” may be pulled up using a 2K pull-up resistor. Since this graphics design
will not have video, the only concern is pulling the bus up to the correct value for the subsystem
ID. The video control signals may be left unconnected. The BIOS interface contains the vendor ID.
The section labeled AGP interface connects directly to the AGP connector. The memory interfaces
connect to memory components. Decoupling for the Intel740 graphics accelerator is shown in the
middle of the schematic page.
VGA Connector P-36
The VGA connector provides the RGB output to a monitor. BIOS and hardware provide support
for plug-and-play capability.
SGRAMS P-37
The SGRAMs shown on this page are labeled as 512Kx32. The schematic pinout is actually
capable of supporting either the 512Kx32 or 256Kx32 SGRAMs. This dual-support connection is
achieved through the following method. The 512Kx32 Jedec standard defines AP on pin 51 which
is address 9. BS is on pin 29 and is also labeled as address 10. Address 8 is on pin 30. The Intel740
contains the AP on its address 8 pin and BS on address 9 pin. Since the 256Kx32 has AP with
graphics accelerator address 8 and on pin 51 along with BS with address 9 on pin 29 and a no
connect on pin 30, either the 512K or the 256K SGRAMs are capable of being supported in the
same design (see Figure 3-22).
Note: It is important to disable the special features of SGRAM. This will make the SGRAM operate as an
SDRAM; thus, making it compatible with the Intel740 graphics accelerator.
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