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Panasonic MN103S - Page 548

Panasonic MN103S
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Record of Changes - 11
9-25 Upper
table
Change 15 14
13 12 11
TMXF
-
TMTGE TMONE TMCLE
0 0
0 0 0
R/W R
R/W R/W
R/W
15 14
13 12 11
TMXF
-
TMTGE TMONE TMCLE
0 0
0 0 1
R R
R/W R/W
R/W
9-38 Table
Setup
Proce-
dure (2)
Change Set the compare/capture register
TM8CA(0x0000A208)=0x09C3
Set the compare/capture register
TM8CA(0x0000A208)=0x0EA5
Descrip-
tion(2)
Change ⋅⋅⋅ The setting is 2499 (0x09C3) due to
2500 counts.
⋅⋅⋅ The setting is 3749 (0x0EA5) due to
3750 counts.
9-41 Table
Setup
Proce-
dure (3)
Change Set the interrupt generation cycle
TM8CA(0x0000A208)=0x4E1F
Set the interrupt generation cycle
TM8CA(0x0000A208)=0x752F
Descrip-
tion(3)
Change ⋅⋅⋅ The setting is 19999 (0x4E1F) due to
20000 counts.
⋅⋅⋅ The setting is 29999 (0x752F) due to
30000 counts.
9-55 Table
Setup
Proce-
dure (2)
Change Set the interrupt generation cycle
TM8CA(0x0000A208)=0x4E1F
Set the interrupt generation cycle
TM8CA(0x0000A208)=0x752F
Descrip-
tion(2)
Change ⋅⋅⋅ The setting is 19999 (0x4E1F) due to
20000
counts.
⋅⋅⋅ The setting is 29999 (0x752F)
due to
30000
counts.
9-61 Line 3 to
6
Change The output pin (TM8AIO) using timer 8
outputs waveforms as shown below
(repeating “L” output for 2
ms and
“H” output for the next 1 ms). IOCLK is
selected as clock source to match the
binary counter and the compare/capture
A
register for every 2 ms and to match
the binary counter and the compare/cap-
ture B
register for every
3 ms.
The output pin (TM8AIO) using timer 8
outputs waveforms as shown below
(repeating “L” output for 1.5
ms and
“H” output for the next 0.5 ms). IOCLK is
selected as clock source to match the
binary counter and the compare/capture
B register for every 1.5
ms and to match
the binary counter and the compare/cap-
ture A register for every
2
ms.
Figure
9.8.3
Change
Table
Setup
Proce-
dure (2)
Change Set the repeating cycle
TM8CA
(0x0000A208)=0x9C3F
Set the repeating cycle
TM8CB(0x0000A20C)=0xAFC7
Descrip-
tion(2)
Change ⋅⋅⋅ The setting is 39999 (0x9C3F) due to
40000 counts.
⋅⋅⋅ The setting is 44999 (0xAFC7) due to
45000 counts.
9-64 Figure
9.9.1
Change
Page Section Definition Previous Edition (Ver.1) New Edition (Ver.1.1)
Output pin
(TM8AIO)
2 ms
3 ms
Output pin
(TM8BIO)
1.5ms
2ms
Caputure input
edge
Binary counter
Compare/capture
register
Interrupt request
flag
Count clock
0008
0000
0006 0007
0008 0003
0003
0000
0001 0002 0001 0002
Edge detection
flag
006 007 008 009 010 000 001 002
010 004
003 004 000 001 002
Caputure input
edge
Binary counter
Compare/capture
register
Interrupt request
flag
Count clock

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