Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 306 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
1
0
HW1
HW0
0
0
R/W
R/W
Delay Cycles from RD, WEn Negation to Address, CSn
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
SDRAM*:
• CS2WCR
Bit Bit Name
Initial
Value R/W Description
31 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 1 R Reserved
This bit is always read as 1. The write value should
always be 1.
9 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
8
7
A2CL1
A2CL0
1
0
R/W
R/W
CAS Latency for Area 2
Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
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