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Segger J-Link - Page 351

Segger J-Link
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J-Link / J-Trace (UM08001) © 2004-2017 SEGGER Microcontroller GmbH & Co. KG
351
12.4.4.6 CPU tab
Instruction set simulation
This enables instruction set simulation which speeds up single stepping instructions
especially when using flash breakpoints.
Reset strategy
This defines the way J-Link RDI should handle resets called by software.
J-Link supports different reset strategies. This is necessary because there is no single
way of resetting and halting an ARM core before it starts to execute instructions.
For more information about the different reset strategies which are supported by J-
Link and why different reset strategies are necessary, please refer to
Reset strategies
on page 199.
12.4.4.7 Log tab
A log file can be generated for the J-Link DLL and for the J-Link RDI DLL. This log
files may be useful for debugging and evaluating. They may help you to solve a prob-
lem yourself, but is also needed by customer support help you.
Default path of the J-Link log file:
c:\JLinkARM.log
Default path of the J-Link RDI log file: c:\JLinkRDI.log

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