Segger J-Link - Page 36

36 CHAPTER 1 Introduction
J-Link / J-Trace (UM08001) ©
2004-2017 SEGGER Microcontroller GmbH & Co. KG
1.3.3.3 Hardware versions
Version 9.1
• Initial design based on STM32F205.
Version 9.2
Identical to version 9.1 with the following exception:
• Pin 1 (VTref) is used for measuring target reference voltage only. Buffers on J-
Link side are no longer powered through this pin but via the J-Link internal volt-
age supplied via USB.
1.3.3.4 Software and Hardware Features Overview
For detailed information about hardware and software features of your J-Link/J-Trace
model and version see:
• https://wiki.segger.com/Software_and_Hardware_Features_Overview
Data output rise time (T
rdo
)T
rdo
<= 10ns
Data output fall time (T
fdo
)T
fdo
<= 10ns
Clock rise time (T
rc
)T
rc
<= 3ns
Clock fall time (T
fc
)T
fc
<= 3ns
Table 1.2: J-Link specifications