DocID018909 Rev 11 11/1731
RM0090 Contents
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11.4 DMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
11.5 DMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
11.5.1 DMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 354
11.5.2 DMA2D Interrupt Status Register (DMA2D_ISR) . . . . . . . . . . . . . . . . 356
11.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 357
11.5.4 DMA2D foreground memory address register (DMA2D_FGMAR) . . . 358
11.5.5 DMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 358
11.5.6 DMA2D background memory address register (DMA2D_BGMAR) . . 359
11.5.7 DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 359
11.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 359
11.5.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 362
11.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 363
11.5.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 365
11.5.12 DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
11.5.13 DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
11.5.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 366
11.5.15 DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 367
11.5.16 DMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 368
11.5.17 DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 369
11.5.18 DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 369
11.5.19 DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 370
11.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR) . 370
11.5.21 DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 373
12.1.1 NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
12.1.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
12.1.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
12.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 373
12.2.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
12.2.2 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
12.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
12.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
12.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 384
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