Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1122/1731 DocID018909 Rev 11
that follows the final nibble. In order to receive the frame correctly, the MII_RX_DV
signal must encompass the frame, starting no later than the SFD field.
• MII_RX_ER: receive error must be asserted for one or more clock periods
(MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere
in the frame. This error condition must be qualified by MII_RX_DV assertion as
described in Table 188.
MII clock sources
To generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked
with an external 25 MHz as shown in Figure 355. Instead of using an external 25 MHz
quartz to provide this clock, the STM32F4xxmicrocontroller can output this signal on its
MCO pin. In this case, the PLL multiplier has to be configured so as to get the desired
frequency on the MCO pin, from the 25 MHz external quartz.
Table 187. TX interface signal encoding
MII_TX_EN MII_TXD[3:0] Description
0 0000 through 1111 Normal inter-frame
1 0000 through 1111 Normal data transmission
Table 188. RX interface signal encoding
MII_RX_DV MII_RX_ERR MII_RXD[3:0] Description
0 0 0000 through 1111 Normal inter-frame
0 1 0000 Normal inter-frame
0 1 0001 through 1101 Reserved
0 1 1110 False carrier indication
0 1 1111 Reserved
1 0 0000 through 1111 Normal data reception
1 1 0000 through 1111 Data reception with errors
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