Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1142/1731 DocID018909 Rev 11
The interrupt register bits only indicate the block from which the event is reported. You have
to read the corresponding status registers and other registers to clear the interrupt. For
example, bit 3 of the Interrupt register, set high, indicates that the Magic packet or Wake-on-
LAN frame is received in Power-down mode. You must read the ETH_MACPMTCSR
Register to clear this interrupt event.
Figure 370. MAC core interrupt masking scheme
33.5.5 MAC filtering
Address filtering
Address filtering checks the destination and source addresses on all received frames and
the address filtering status is reported accordingly. Address checking is based on different
parameters (Frame filter register) chosen by the application. The filtered frame can also be
identified: multicast or broadcast frame.
Address filtering uses the station's physical (MAC) address and the Multicast Hash table for
address checking purposes.
Unicast destination address filter
The MAC supports up to 4 MAC addresses for unicast perfect filtering. If perfect filtering is
selected (HU bit in the Frame filter register is reset), the MAC compares all 48 bits of the
received unicast address with the programmed MAC address for any match. Default
MacAddr0 is always enabled, other addresses MacAddr1–MacAddr3 are selected with an
individual enable bit. Each byte of these other addresses (MacAddr1–MacAddr3) can be
masked during comparison with the corresponding received DA byte by setting the
corresponding Mask Byte Control bit in the register. This helps group address filtering for the
DA. In Hash filtering mode (when HU bit is set), the MAC performs imperfect filtering for
unicast addresses using a 64-bit Hash table. For hash filtering, the MAC uses the 6 upper
CRC (see note 1 below) bits of the received destination address to index the content of the
Hash table. A value of 000000 selects bit 0 in the selected register, and a value of 111111
selects bit 63 in the Hash Table register. If the corresponding bit (indicated by the 6-bit CRC)
is set to 1, the unicast frame is said to have passed the Hash filter; otherwise, the frame has
failed the Hash filter.
Note: This CRC is a 32-bit value coded by the following polynomial (for more details refer to
Section 33.5.3: MAC frame reception):
AND
AND
OR
TSTI
PMTI
Interrupt
TSTS
PMTS
PMTIM
ai15637
TSTIM
Gx() x
32
x
26
x
23
x
22
x
16
x
12
x
11
x
10
x
8
x
7
x
5
x
4
x
2
x1+ + + + + + + +++++++=
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