DocID018909 Rev 11 59/1731
RM0090 Memory and bus architecture
112
2 Memory and bus architecture
2.1 System architecture
In STM32F405xx/07xx and STM32F415xx/17xx, the main system consists of 32-bit
multilayer AHB bus matrix that interconnects:
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Eight masters:
–Cortex
®
-M4 with FPU core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
– Ethernet DMA bus
– USB OTG HS DMA bus
• Seven slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM1 (112 KB)
– Auxiliary internal SRAM2 (16 KB)
– AHB1 peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
–FSMC
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. The 64-
Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be
accessed only through the CPU. This architecture is shown in Figure 1.
To Next Page
Loading...
Need help?
General