Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1120/1731 DocID018909 Rev 11
Figure 353. MDIO timing and frame structure - Read cycle
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 186 shows how to set the clock ranges.
33.4.2 Media-independent interface: MII
The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
Table 186. Clock range
Selection HCLK clock MDC clock
000 60-100 MHz AHB clock / 42
001 100-150 MHz AHB clock / 62
010 20-35 MHz AHB clock / 16
011 35-60 MHz AHB clock / 26
100 150-180 MHz AHB clock / 102
101, 110, 111 Reserved -
MDC
MDIO
32 1's 0 1 1 0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
D15 D14
D1 D0
Preamble
Start
of
frame
OP
code
PHY address Register address
Turn
around
data
Data to PHY
ai15627
Data from PHY
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