EasyManuals Logo

STMicroelectronics STM32F407 User Manual

STMicroelectronics STM32F407
1731 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #150 background imageLoading...
Page #150 background image
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090
150/1731 DocID018909 Rev 11
6 Reset and clock control for
STM32F42xxx and STM32F43xxx (RCC)
6.1 Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
6.1.1 System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 4).
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see Software reset)
5. Low-power management reset (see Low-power management reset)
Software reset
The reset source can be identified by checking the reset flags in the RCC clock control &
status register (RCC_CSR).
The SYSRESETREQ bit in Cortex
®
-M4 with FPU Application Interrupt and Reset Control
Register must be set to force a software reset on the device. Refer to the Cortex
®
-M4 with
FPU technical reference manual for more details.
Low-power management reset
There are two ways of generating a low-power management reset:
1. Reset generated when entering the Standby mode:
This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.
In this case, whenever a Standby mode entry sequence is successfully executed, the
device is reset instead of entering the Standby mode.
2. Reset when entering the Stop mode:
This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.
In this case, whenever a Stop mode entry sequence is successfully executed, the
device is reset instead of entering the Stop mode.
6.1.2 Power reset
A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset
2. When exiting the Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 4)

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the STMicroelectronics STM32F407 and is the answer not in the manual?

STMicroelectronics STM32F407 Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F407
CategoryController
LanguageEnglish

Related product manuals