Debug support (DBG) RM0090
1678/1731 DocID018909 Rev 11
38.6.2 Boundary scan TAP
JTAG ID code
The TAP of the STM32F4xx BSC (boundary scan) integrates a JTAG ID code equal to .
• 0x06413041 for STM32F405xx/07xx and STM32F415xx/17xx devices
• 0x06419041 for STM32F42xxx and STM32F43xxx devices
38.6.3 Cortex
®
-M4 with FPU TAP
The TAP of the ARM
®
Cortex
®
-M4 with FPU integrates a JTAG ID code. This ID code is the
ARM
®
default one and has not been modified. This code is only accessible by the JTAG
Debug Port.
This code is 0x4BA00477 (corresponds to Cortex
®
-M4 with FPU r0p1, see Section 38.2:
Reference ARM® documentation).
38.6.4 Cortex
®
-M4 with FPU JEDEC-106 ID code
The ARM
®
Cortex
®
-M4 with FPU integrates a JEDEC-106 ID code. It is located in the 4KB
ROM table mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
38.7 JTAG debug port
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex
®
-M4 with FPU r0p1 Technical Reference
Manual (TRM), for references, please see
Section 38.2: Reference ARM® documentation).
Table 295. JTAG debug port data registers
IR(3:0) Data register Details
1111
BYPASS
[1 bit]
1110
IDCODE
[32 bits]
ID CODE
0x4BA00477 (ARM
®
Cortex
®
-M4 with FPU r0p1 ID Code)
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