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DocID018909 Rev 11 521/1731

RM0090 Advanced-control timers (TIM1&TIM8)

581

Figure 98. Counter timing diagram, internal clock divided by N

Figure 99. Counter timing diagram, update event when repetition counter

is not used

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-

reload value down to 1 and generates a counter underflow event. Then it restarts counting

from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to

'00'. The Output compare interrupt flag of channels configured in output is set when: the

counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center

aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,

CMS = "11").

In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated

by hardware and gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter underflow

or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode

controller) also generates an update event. In this case, the counter restarts counting from

0, as well as the counter of the prescaler.

Timer clock = CK_CNT

Counter register

Update interrupt flag (UIF)

Counter underflow

Update event (UEV)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register

Update interrupt flag (UIF)

Counter underflow

Update event (UEV)

35 34 33 32 31 30 2F04 03 02 01 0005

Auto-reload register

FF 36

Write a new value in TIMx_ARR

STMicroelectronics STM32F407 User Manual

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