Chrom-Art Accelerator™ controller (DMA2D) RM0090
362/1731 DocID018909 Rev 11
11.5.9 DMA2D foreground color register (DMA2D_FGCOLR)
Address offset: 0x0020
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
RED[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN[7:0] BLUE[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value
Bits 23:16 RED[7: 0]: Red Value
These bits defines the red value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Bits 15:8 GREEN[7: 0]: Green Value
These bits defines the green value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
Bits 7:0 BLUE[7: 0]: Blue Value
These bits defines the blue value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
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