Chrom-Art Accelerator™ controller (DMA2D) RM0090
366/1731 DocID018909 Rev 11
11.5.13 DMA2D background CLUT memory address register
(DMA2D_BGCMAR)
Address offset: 0x0030
Reset value: 0x0000 0000
11.5.14 DMA2D output PFC control register (DMA2D_OPFCCR)
Address offset: 0x0034
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31: 0 MA[31: 0]: Memory address
Address of the data used for the CLUT address dedicated to the background image.
This register can only be written when no transfer is on going. Once the CLUT transfer
has started, this register is read-only.
If the background CLUT format is 32-bit, the address must be 32-bit aligned.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CM[2:0]
rw rw rw
Bits 31: 3 Reserved, must be kept at reset value
Bits 2: 0 CM[2: 0]: Color mode
These bits define the color format of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
others: meaningless
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