DocID018909 Rev 11 833/1731
RM0090 Inter-integrated circuit (I
2
C) interface
864
Figure 240. I
2
C block diagram for STM32F42x/43x
1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.
27.3.2 I
2
C slave mode
By default the I
2
C interface operates in Slave mode. To switch from default Slave mode to
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
• 2 MHz in Sm mode
• 4 MHz in Fm mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
$ATASHIFTREGISTER
#OMPARATOR
/WNADDRESSREGISTER
#LOCKCONTROL
3TATUSREGISTERS
#ONTROLREGISTERS
#ONTROL
#LOCK
CONTROL
$ATA
CONTROL
3#,
LOGIC
$UALADDRESSREGISTER
$ATAREGISTER
0%#REGISTER
)NTERRUPTS
0%#CALCULATION
3-"!
3$!
2EGISTER##2
3232
#2#2
$-!REQUESTS!#+
-36
.OISE
FILTER
.OISE
FILTER
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