Chrom-Art Accelerator™ controller (DMA2D) RM0090
342/1731 DocID018909 Rev 11
11.2 DMA2D main features
The main DMA2D features are:
• Single AHB master bus architecture.
• AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT
accesses which are 32-bit).
• User programmable working area size
• User programmable offset for sources and destination areas
• User programmable sources and destination addresses on the whole memory space
• Up to 2 sources with blending operation
• Alpha value can be modified (source value, fixed value or modulated value)
• User programmable source and destination color format
• Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct
color coding
• 2 internal memories for CLUT storage in indirect color mode
• Automatic CLUT loading or CLUT programming via the CPU
• User programmable CLUT size
• Internal timer to control AHB bandwidth
• 4 operating modes: register-to-memory, memory-to-memory, memory-to-memory with
pixel format conversion, and memory-to-memory with pixel format conversion and
blending
• Area filling with a fixed color
• Copy from an area to another
• Copy with pixel format conversion between source and destination images
• Copy from two sources with independent color format and blending
• Abort and suspend of DMA2D operations
• Watermark interrupt on a user programmable destination line
• Interrupt generation on bus error or access conflict
• Interrupt generation on process completion
11.3 DMA2D functional description
11.3.1 General description
The DMA2D controller performs direct memory transfer. As an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
The DMA2D can operate in the following modes:
• Register-to-memory
• Memory-to-memory
• Memory-to-memory with Pixel Format Conversion
• Memory-to-memory with Pixel Format Conversion and Blending
The AHB slave port is used to program the DMA2D controller.
The block diagram of the DMA2D is shown in Figure 40: DMA2D block diagram.
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