Independent watchdog (IWDG) RM0090
700/1731 DocID018909 Rev 11
with a different value will break the sequence and register access will be protected again.
This implies that it is the case of the reload operation (writing 0xAAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
21.3.3 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M4 with FPU core halted), the IWDG
counter either continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module. For more details, refer to
Section 38.16.2: Debug support
for timers, watchdog, bxCAN and I2C.
Figure 213. Independent watchdog block diagram
Note: The watchdog function is implemented in the V
DD
voltage domain that is still functional in
Stop and Standby modes.
)7$'RESET
PRESCALER
)7$'?02
0RESCALERREGISTER
)7$'?2,2
2ELOADREGISTER
BIT
,3)
K(Z
)7$'?+2
+EYREGISTER
#/2%
6$$VOLTAGEDOMAIN
)7$'?32
3TATUSREGISTER
-36
BITRELOADVALUE
BITDOWNCOUNTER
Table 106. Min/max IWDG timeout period at 32 kHz (LSI)
(1)
1. These timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Please
refer to the LSI oscillator characteristics table in the device datasheet for maximum and minimum values.
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4 0 0.125 512
/8 1 0.25 1024
/16 2 0.5 2048
/32 3 1 4096
/64 4 2 8192
/128 5 4 16384
/256 6 8 32768
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