STMicroelectronics STM32F407 User Manual

DocID018909 Rev 11 183/1731
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
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6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
Bit 5 HASHEN: Hash modules clock enable
This bit is set and cleared by software.
0: Hash modules clock disabled
1: Hash modules clock enabled
Bit 4 CRYPEN: Cryptographic modules clock enable
This bit is set and cleared by software.
0: cryptographic module clock disabled
1: cryptographic module clock enabled
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DCMIEN: Camera interface enable
This bit is set and cleared by software.
0: Camera interface clock disabled
1: Camera interface clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FMCEN
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 FMCEN: Flexible memory controller module clock enable
This bit is set and cleared by software.
0: FMC module clock disabled
1: FMC module clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART8
EN
UART7
EN
DAC
EN
PWR
EN
Reser-
ved
CAN2
EN
CAN1
EN
Reser-
ved
I2C3
EN
I2C2
EN
I2C1
EN
UART5
EN
UART4
EN
USART
3
EN
USART
2
EN
Reser-
ved
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Reserved
WWDG
EN
Reserved
TIM14
EN
TIM13
EN
TIM12
EN
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw rw rw rw rw rw rw rw rw rw rw rw

STMicroelectronics STM32F407 Specifications

General

Brand	STMicroelectronics
Model	STM32F407
Category	Controller
Language	English