STMicroelectronics STM32F407 User Manual

Memory and bus architecture RM0090
62/1731 DocID018909 Rev 11
Figure 2. System architecture for STM32F42xxx and STM32F43xxx devices
2.1.1 I-bus
This bus connects the Instruction bus of the Cortex
®
-M4 with FPU core to the BusMatrix.
This bus is used by the core to fetch instructions. The target of this bus is a memory
containing code (internal Flash memory/SRAM or external memories through the
FSMC/FMC).
2.1.2 D-bus
This bus connects the databus of the Cortex
®
-M4 with FPU to the 64-Kbyte CCM data RAM
to the BusMatrix. This bus is used by the core for literal load and debug access. The target
of this bus is a memory containing code or data (internal Flash memory or external
memories through the FSMC/FMC).
2.1.3 S-bus
This bus connects the system bus of the Cortex
®
-M4 with FPU core to a BusMatrix. This
bus is used to access data located in a peripheral or in SRAM. Instructions may also be
fetched on this bus (less efficient than ICode). The targets of this bus are the internal
SRAM1, SRAM2 and SRAM3, the AHB1 peripherals including the APB peripherals, the
AHB2 peripherals and the external memories through the FSMC/FMC.
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STMicroelectronics STM32F407 Specifications

General

Brand	STMicroelectronics
Model	STM32F407
Category	Controller
Language	English