Serial audio interface (SAI) RM0090
942/1731 DocID018909 Rev 11
If there is an audio block in the SAI synchronous with the other one, the one which is the
master must be disabled first.
29.16 SAI DMA interface
In order to free the CPU and to optimize the bus bandwidth, each SAI audio block has an
independent DMA interface in order to read or to write into the SAI_xDR register (to hit the
internal FIFO). There is one DMA channel per audio block following basic DMA
request/acknowledge protocol.
To configure the audio block to transfer through the DMA interface, set bit DMAEN in the
SAI_xCR1 register. The DMA request is managed directly by the FIFO controller depend of
FIFO threshold level (for more details please refer to Internal FIFOs section). DMA direction
is linked to the SAI audio block configuration:
• If the audio block is a transmitter, the audio block’s FIFO controller outputs a DMA
request to load the FIFO with data written in the SAI_xDR register.
• If the audio block is a receiver, the DMA request will concern read operations from the
SAI_xDR register.
Below are the SAI configuration steps followed when DMA is used:
1. Configure SAI and FIFO Threshold level (in order to specify when the DMA request to
be launched)
2. Configure SAI DMA channel
3. Enable DMA
4. Enable SAI
Note: Before configuring the SAI block, the SAI DMA channel must be disabled.
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